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IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O
* Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * CMOS power levels (0.4 W typ. static) * All inputs, outputs, and I/O are 5V tolerant * Supports hot insertion * Available in SSOP, TSSOP, and TVSOP packages
IDT74LVC16646A
FEATURES:
DESCRIPTION:
DRIVE FEATURES: APPLICATIONS:
* High Output Drivers: 24mA * Reduced system switching noise
* 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems
The LVC16646A 16-bit bus transceiver/register is built using advanced dual metal CMOS technology. This high-speed, low power device is organized as two independent 8-bit D-type transceivers with 3-state D-type registers. The control circuitry is organized for multiplexed transmission of data between the A bus and B bus either directly or from the internal storage registers. Each 8-bit transceiver/register features direction control (DIR), over-riding Output Enable control (OE) and Select lines (SAB and SBA) to select either real-time data or stored data. Separate clock inputs are provided for A and B port registers. Data on the A or B data bus, or both, can be stored in the internal registers by the low-to-high transitions at the appropriate clock pins. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVC16646A has been designed with a 24mA output driver. The driver is capable of driving a moderate to heavy load while maintaining speed performance.
FUNCTIONAL BLOCK DIAGRAM
56
29
1OE 1DIR
1 55 54 2
2OE
28 30 31 27 26
2DIR 2CLKBA 2SBA 2CLKAB
1CLKBA 1SBA 1CLKAB 1SAB
3
B REG 1D C1
2SAB
B REG 1D C1
1A1
5
A REG 1D C1
52
1B1
2A1
15
A REG 1D C1
42
2B1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 1999 Integrated Device Technology, Inc.
APRIL 1999
DSC-4488/2
IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1DIR 1CLKAB
1SAB
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND -0.5 to +6.5 -65 to +150 -50 to +50 -50 100
Unit V C mA mA mA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OE 1CLKBA
1SBA
TSTG IOUT IIK IOK ICC ISS
GND
1A1 1A2
GND
1B1 1B2
VCC
1A3 1A4 1A5
VCC
1B3 1B4 1B5
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
GND
1A6 1A7 1A8 2A1 2A2 2A3
GND
1B6 1B7 1B8 2B1 2B2 2B3
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 6.5 6.5 Max. 6 8 8 Unit pF pF pF
NOTE: 1. As applicable to the device type.
GND
2A4 2A5 2A6
GND
2B4 2B5 2B6
VCC
2A7 2A8
VCC
2B7 2B8
PIN DESCRIPTION
Pin Names xAx xBx xCLKAB, xCLKBA xSAB, xSBA xOE xDIR Description Data Register A Inputs Data Register B 3-State Outputs Data Register B Inputs Data Register A 3-State Outputs Clock Pulse Inputs Output Data Source Select Inputs Output Enable Inputs Direction Control Inputs
GND
2SAB 2CLKAB 2DIR
GND
2SBA 2CLKBA 2OE
SSOP/ TSSOP/ TVSOP TOP VIEW
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IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE(1)
Inputs xOE X X H H L L L L xDIR X X X X L L H H xCLKAB X H or L X X X H or L xCLKBA X H or L X H or L X X xSAB X X X X X X L H xSBA X X X X L H X X xAx Input Unspecified(2) Input Input Output Output Input Input Data I/O
(2)
xBx Unspecified Input Input Input Input Input Output Output
(2)
Operation or Function Store A, B unspecified(2) Store A, B unspecified(2) Store A and B data Isolation, hold storage Real time B data to A bus Stored B data to A bus Real time A data to B bus Stored A data to B bus
NOTES: 1. H = HIGH Voltage Level X = Don't Care L = LOW Voltage Level = LOW-to-HIGH transition 2. The data output functions may be enabled or disabled by various signals at the xOE or xDIR inputs. Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC -- -- -- -- -- -- -- -0.7 100 -- -- -- 50 -1.2 -- 10 10 500 A V mV A VCC = 3.6V VO = 0 to 5.5V -- -- 10 A Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VI = 0 to 5.5V Test Conditions Min. 1.7 2 -- -- -- Typ.(1) -- -- -- -- -- Max. -- -- 0.7 0.8 5 A V Unit V
Quiescent Power Supply Current Variation
3.6 VIN 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND
A
NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. This applies in the disabled state only.
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IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
INDUSTRIAL TEMPERATURE RANGE
BUS A
BUS B
BUS A
BUS B
xDIR L
xOE L
xCLKAB X
xCLKBA X
xSAB X
xSBA L
xDIR H
xOE L
xCLKAB X
xCLKBA X
xSAB L
xSBA X
REAL-TIME TRANSFER BUS B TO A
REAL-TIME TRANSFER BUS A TO B
BUS A
BUS B
BUS A
BUS B
xDIR X X X
xOE X X H
xCLKAB X
xCLKBA X
xSAB X X X
xSBA X X X
xDIR L H
(1)
xOE L L
xCLKAB X H or L
xCLKBA H or L X
xSAB X H
xSBA H X
STORAGE FROM A, B, OR A AND B
TRANSFER STORED DATA TO A AND/OR B
NOTE: 1. Cannot transfer data to A Bus and B Bus simultaneously.
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IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD CPD Parameter Power Dissipation Capacitance per Transceiver Outputs enabled Power Dissipation Capacitance per Transceiver Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 60 12 Unit pF
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IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tSU tH tW tSK(o) Propagation Delay xAx to xBx or xBx to xAx Propagation Delay CLKBA to xAx, CLKAB to xBx Propagation Delay xSBA or xSAB to xAx or xBx Output Enable Time xOE to xAx or Bx Output Enable Time xDIR to xAx or Bx Output Disable Time xOE to xAx or Bx Output Disable Time xDIR to xAx or Bx Set-up Time HIGH or LOW xAx or xBx before CLKAB or CLKBA Hold Time HIGH or LOW xAx or xBx after CLKAB or CLKBA Clock Pulse Width HIGH or LOW Output Skew(2) 3.3 -- 3.3 -- 500 ns ps -- -- 0.3 -- ns 3.2 -- 2.9 -- ns -- 7.8 2 7 ns -- 7.7 2.1 6.9 ns -- 8.5 1.4 7.2 ns -- 8.5 1.3 6.9 ns -- 9.2 1.7 7.7 ns -- 7.9 1.8 6.7 ns Parameter Min. 150 -- Max. -- 6.8 VCC = 3.3V 0.3V Min. 150 1.3 Max. -- 5.7 Unit MHz ns
--
--
--
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
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IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 Pulse (1, 2) Generator VIN D.U.T. RT 500 CL
LVC Link
VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
VLOAD Open GND
6 2.7 1.5 300 300 50
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
LVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VOL+VLZ VOL VOH VOH-VHZ 0V
LVC Link
VOUT
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
VIH VT 0V VOH VT VOL VOH VT VOL tPLH2 tPHL2
LVC Link
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC Link
INPUT
Set-up, Hold, and Release Times
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE VT
LVC Link
tPLH1
tPHL1
OUTPUT 1
VT
tSK (x)
tSK (x)
OUTPUT 2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Pulse Width
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
X LVC IDT XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package
PV PA PF
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package
646A 16-Bit Bus Transceiver/Register 16 Blank 74 Double-Density with Resistors, 24mA No Bus-hold -40C to +85C
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